The present invention relates to a method for fabricating a capacitor of a semiconductor device, and more particularly to a method for forming a storage node electrode of a MIM (Metal-Insulator-Metal) capacitor of a semiconductor device.
Currently, according to a method by which a contact plug for forming a general MIM stack TiN storage node electrode in a DRAM having an integration degree of 128 Megabit is formed, a bit line is formed on a substrate on which a semiconductor circuit of a transistor including a metal or silicide layer-oxide-semiconductor, etc. is formed, and an insulation layer is formed, and then a storage node contact hole is formed. The storage node contact has a lower portion including a silicon substrate, and doped silicon or silicon grown by an epitaxial method. Then, after the interior of the storage node contact is filled with polysilicon by using a chemical vapor deposition method, a storage node contact plug is manufactured by shorting it by CMP or etchback.
FIGS. 1A to 1E are process cross-sectional views for explaining a conventional method for forming a capacitor of a semiconductor device.
First, as shown in FIG. 1A, after a first oxide layer 3 is formed on a semiconductor substrate 1 having a gate electrode, a source/drain, etc., a storage node contact 4 exposing the source or the drain is formed by selectively etching the first oxide layer 3. A first silicon nitride layer (not shown) is deposited on the substrate having the storage node contact 4, and then a spacer 5 surrounding the inner side wall of the storage node contact 4 is formed by etching the silicon nitride layer. Thereafter, a polysilicon layer is deposited on the resulting structure, so as to fill the storage node contact 4 including the spacer 5, and then a storage node plug 7 is formed by etching the polysilicon layer. Then, after a second silicon nitride layer 9 is deposited on overall surface of the substrate including the storage node plug 7, so as to have a thickness of 500 to 1500 Å, a second oxide layer 11 is formed on the second silicon nitride layer 9, so as to have a thickness of 15000 to 30000 Å. Here, the second silicon nitride layer 9 functions as an etch stop layer in an etching step for forming a hole to be formed a storage node electrode of a capacitor, and the second oxide layer 11 functions as a sacrificial oxide layer for forming the storage node electrode.
Next, as shown in FIG. 1B, after a second oxide layer is etched until the second silicon nitride layer 9 is exposed, the hole 12 is formed by selectively etching the second silicon nitride layer 9. At this time, a portion of the spacer 5 is etched in the step of etching the second silicon nitride layer.
Thereafter, as shown in FIG. 1C, a cleaning step 13 is performed to the etching resultant.
FIGS. 1A to 1E are process cross-sectional views for explaining a conventional method for forming a capacitor of a semiconductor device.
First, as shown in FIG. 1A, after a first oxide layer 3 is formed on a semiconductor substrate 1 having a gate electrode, a source/drain, etc., a storage node contact 4 exposing the source or the drain is formed by selectively etching the first oxide layer 3. A first silicon nitride layer (not shown) is deposited on the substrate having the storage node contact 4, and then a spacer 5 surrounding the inner side wall of the storage node contact 4 is formed by etching the silicon nitride layer. Thereafter, a polysilicon layer is deposited on the resulting structure, so as to fill the storage node contact 4 including the spacer 5, and then a storage node plug 7 is formed by etching the polysilicon layer. Then, after a second silicon nitride layer 9 is deposited on overall surface of the substrate including the storage node plug 7, so as to have a thickness of 500 to 1500 Å, a second oxide layer 11 is formed on the second silicon nitride layer 9, so as to have a thickness of 15000 to 30000 Å. Here, the second silicon nitride layer 9 functions as an etch stop layer in an etching step for forming a hole to be formed a storage node electrode of a capacitor, and the second oxide layer 11 functions as a sacrificial oxide layer for forming the storage node electrode.
Next, as shown in FIG. 1B, after a second oxide layer is etched until the second silicon nitride layer 9 is exposed, the hole 12 is formed by selectively etching the second silicon nitride layer 9. At this time, a portion of the spacer 5 is etched in the step of etching the second silicon nitride layer.
Thereafter, as shown in FIG. 1C, a cleaning step 13 is performed to the etching resultant.
Then, as shown in FIG. 1D, after a Ti layer (not shown) is deposited on the substrate in which the cleaning step is completed by a CVD or PVD process so as to have a thickness of 50 Å, a TiSix layer 15 is formed by proceeding an annealing step. Here, the TiSix layer 15 is formed by the reaction of the Ti layer with silicon within the storage node plug 7. Thereafter, the Ti layer which is not reacted is removed by a wet etching step, thereby lowering the resistance of the contact surface between the storage node plug 7 and a TiN layer (not shown) for the storage node electrode to be formed thereafter.
Next, as shown in FIG. 1E, the TiN layer (not shown) for the storage node electrode is deposited on the overall surface of the substrate having the TiSix layer 15, and then a storage node electrode S1 of the capacitor electrically connected to the storage node plug 7 through the TiSix layer 15 is formed by etchback the TiN layer. Thereafter, the manufacturing process of the capacitor is completed by sequentially forming the dielectric layer 17 and the TiN layer 19 for the plate electrode on the storage node electrode S1 of the capacitor.
FIG. 2 is a TEM picture for explaining problems of the conventional art.
In the conventional art, during the etching step for forming the hole, as shown in FIG. 2, the spacer on the side wall of the storage node plug is attacked and thus a crevasse results. The width of the upper portion of the crevasse ranges from 300 to 400 Å. Thereafter, since the TiN layer having a thickness of 50 Å and the dielectric layer having the thickness of 50 to 100 Å is formed sequentially on the overall surface of the substrate in which the crevasse has formed, the crevasse is closed or narrowed at the time of deposition of the TiN layer for the plate electrode. Therefore, since the TiN layer for the plate electrode is not deposited properly, a cusp or a structural defect which serves as a cause of the leakage current of the capacitor is formed in the dielectric layer or the TiN layer for the plate electrode.
While testing the capacitor at a device level, the capacitor may fail due to the current leakage. If such a phenomenon occurs, the corresponding cell immediately fails, and the corresponding chip has a high possibility of failing. In the case that a polysilicon layer is applied as a material for the storage node electrode, even though the crevasse is formed, since the step coverage characteristics of the polysilicon layer is excellent, the crevasse is filled nicely. On the other hand, in case of the MIM capacitor, since a metal is applied as the material for the storage node electrode, even when depositing by the ALD method, the step coverage characteristics of the metal layer is inferior to that of the polysilicon, the crevasse generally cannot be filled as well.